The "AutoPhi" project is an ambitious end-to-end initiative to design, verify, and manufacture a family of specialized chips for AI acceleration. This isn't just a single chip, but a portfolio of solutions targeting different performance and cost points, telling a complete story from architectural concept to physical product.The project is organized into three main product lines, each with a standard and a high-performance or economy variant:
AutoPhi_Project & AutoPhi_Project - Economy: This is the foundational design. It's a System-on-Chip (SoC) built around a high-speed PCIe Gen5 interface to communicate with a host computer. The rtl (hardware design files) folder contains the Verilog code for the core components we have been building: the PCIe controller, TLP logic, DMA engine, AXI interconnect, and memory controller. The - Economy version is a cost-optimized variant of this base design, likely for more power-efficient or entry-level applications.
AutoPhi_GPU & AutoPhi_GPU - Perfomance: This product line integrates a powerful Graphics Processing Unit (GPU) into the base architecture. It targets more demanding parallel processing tasks common in both graphics and general-purpose AI workloads. The - Performance variant is likely tuned with higher clock speeds, more cores, or faster memory interfaces to deliver maximum throughput.
AutoPhi_Ai-AFF & AutoPhi_Ai-AFF - Performance: This is the most advanced and specialized product line. "AFF" likely stands for "AI Acceleration Fabric." This suggests it moves beyond a standard GPU, incorporating a custom, highly specialized hardware architecture—detailed in files like ADVANCED_LAYER_SPECS.md—designed specifically to accelerate the complex mathematical operations at the heart of modern AI models.
Across all these projects, the folder structure reveals a complete, professional silicon engineering workflow:
Design & Architecture (rtl, docs): The core logic of the chips is defined in Verilog within the rtl folders. The vision and specifications are captured in the docs and architecture markdown files.
Verification & Testing (tb, verification, sim): Each piece of hardware is rigorously tested. The tb (testbench) and verification folders contain the code to simulate the design and ensure it's free of bugs. We've spent most of our time in this stage.
Physical Implementation (physical_design, pcb, constraints, openlane): This is where the digital design becomes a physical object. These folders hold the instructions (constraints) and files for turning the Verilog code into a real-world chip layout (physical_design, openlane) and placing that chip onto a printed circuit board (pcb).
Software & Handoff (software, foundry_delivery): A chip is useless without software. The software directory contains the necessary drivers and applications to make the hardware function. Finally, the foundry_delivery zip files are the complete packages sent to a manufacturer (like Intel, based on the filenames) to produce the final silicon wafers.
In essence, your workspace tells the story of creating a diverse family of AI accelerators, from the first line of code to a market-ready product, with different versions engineered to dominate every segment from low-cost edge devices to high-performance data center servers.