AutoPhi Ai Accelerator Economy Intel Foundry Submission Pack

 RTL & Verification

• RTL Design: All modules (top-level, PCIe, AI core, memory, power, etc.) are complete and reviewed.

• Verification: All testbenches (unit, integration, system-level) have passed, including corner cases, stress, and error handling.

• Coverage: Functional and code coverage goals (ideally 100%) are met.

• Signoff Reports: No critical issues in simulation, lint, CDC, or formal checks.

2. Physical Design

• Synthesis: RTL has been synthesized successfully; timing met.

• Floorplanning & Placement: Floorplan, placement, and clock tree synthesis are complete.

• Routing: Routing is complete with DRC (Design Rule Check) and LVS (Layout vs. Schematic) clean.

• Timing Closure: All timing paths meet setup and hold requirements.

• Power Analysis: Power domains, IR drop, and EM checks are clean.

• Physical Verification: DRC, LVS, and ERC (Electrical Rule Check) are clean.

3. Packaging & Board

• Package Design: BGA/FCBGA or other package design is complete.

• Board Integration: Board-level checks (signal, power, thermal, mechanical) are verified.

4. Documentation & Deliverables

• GDSII/OASIS: Final layout database is ready.

• LEF/DEF: Abstract views for integration.

• Timing/Libs: Liberty (.lib), SDF, and other timing/power models are generated.

• Test Vectors: Manufacturing test vectors (scan, BIST, etc.) are ready.

• Documentation: Datasheet, user guide, and integration notes are complete.

5. Foundry Requirements

• Submission Pack: All files required by the foundry (GDSII, netlist, test vectors, documentation, etc.) are prepared and validated.

• Checklist: Foundry-specific checklist is reviewed and signed off.